(1) Field of the Invention
The invention relates to a method of improving step coverage of a dielectric layer over metal lines, and more particularly, to a method of improving step coverage of a dielectric layer over metal lines by surrounding the metal lines with trenches and dummy metal island areas in the fabrication of integrated circuits.
(2) Description of the Prior Art
Conventional metal layout is function dominated and metal lines are located at random. Metal line spacings vary considerably. Therefore, step coverage of subsequent intermetal dielectric or passivation layers is inevitably unacceptable. The resulting bad planarization causes reliability problems. Referring to FIG. 1, there is shown a top plan view of metal lines of the prior art. Metal lines 20 and 22 have been formed overlying insulating layer 16. View 2--2 of FIG. 1 is shown in FIG. 2 as a cross-section. When dielectric or passivation layer 28 is deposited over the metal lines 20 and 22, the layer is not planarized especially between widely spaced metal lines 20 and 22. This results in bad step coverage of the overlayers. The step coverage of the passivation layer on high aspect ratio metal lines is very poor--less than 40%. In addition, the large step height will challenge the depth of focus of photolithography and thus narrow the process window. Moreover, etching residue for the overlayer is easily formed at the bottom corner 34, causing a stringer problem.
Keyhole type tunnels 30 are formed within the dielectric layer between metal lines with spacing smaller than about 1 micrometer. These tunnels open up at metal line terminals, at points where the underlying metal layer is absent, and at turns in metal lines. During resist coating, the resist sinks into the underlying tunnels, making the resist layer thinner in these areas. The thinner resist generates holes in the passivation layer after pad etch which then degrades reliability. The sunken resist also causes a resist residue problem.
U.S. Pat. No. 5,032,890 to Ushiku et al describes the formation of dummy lines for improved next level coverage of an interconnection layer.